1. Field of the Invention
This application is related to integrated circuits and more particularly to data communications links between integrated circuits.
2. Description of the Related Art
To properly recover data received by an integrated circuit node transmitted across a data communications link by another integrated circuit node, the receiving node must sample the data during an appropriate phase of the data signal. A transmitting node compliant with an exemplary communications link may transmit, on a separate signal line, a reference clock for use in sampling commands, addresses or data (hereinafter, “data”) by the receiving node. However, introduction of skew between received data and a received sample clock (e.g., skew introduced by the channel of the communications link, the receiver, or other sources) may compromise data recovery. For example, if skew between the reference clock and the received data causes data transitions to approach the sampling point, the data transitions may fall within the clock setup time of a sampling device (e.g., flip flop or other state element) causing errors in data recovery. In addition, the phase relationship between the received clock signal and the received data signal may not be stationary, which adds complexity to clock and data recovery operations. Accordingly, techniques for maintaining the integrity of data recovered by a receiving node on a data communications link are desired.